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MC74HCT541A Octal 3-State Non-Inverting Buffer/Line Driver/ Line Receiver With LSTTL-Compatible Inputs
High-Performance Silicon-Gate CMOS
The MC74HCT541A is identical in pinout to the LS541. This device may be used as a level converter for interfacing TTL or NMOS outputs to high speed CMOS inputs. The HCT541A is an octal non-inverting buffer/line driver/line receiver designed to be used with 3-state memory address drivers, clock drivers, and other bus-oriented systems. This device features inputs and outputs on opposite sides of the package and two ANDed active-low output enables.
Features http://onsemi.com MARKING DIAGRAMS
PDIP-20 N SUFFIX CASE 738
20 MC74HCT541AN AWLYYWWG 1
1
* * * * * * * *
20 SOIC-20WB DW SUFFIX CASE 751D HCT541A AWLYYWWG
Output Drive Capability: 15 LSTTL Loads TTL/NMOS-Compatible Input Levels Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1mA In Compliance With the JEDEC Standard No. 7A Requirements Chip Complexity: 134 FETs or 33.5 Equivalent Gates Pb-Free Packages are Available*
LOGIC DIAGRAM
A1 A2 A3 A4 A5 A6 A7 A8 Output Enables OE1 OE2 2 3 4 5 6 7 8 9 1 19 PIN 20 = VCC PIN 10 = GND 18 17 16 15 14 13 12 11 Y1 Y2 Y3 Y4 Y5
1 1 20 HCT 541A ALYWG G 1 1 20 74HCT541A AWLYWWG 1 1
TSSOP-20 DT SUFFIX CASE 948E
SOEIAJ-20 F SUFFIX CASE 967 Non-Inverting Outputs
Data Inputs
Y6 Y7 Y8
A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
1
June, 2006 - Rev. 5
Publication Order Number: MC74HCT541A/D
MC74HCT541A
PINOUT: 20-LEAD PACKAGES
VCC 20 OE2 19 Y1 18 Y2 17 Y3 16 Y4 15 Y5 14 Y6 13 Y7 12 Y8 11 OE1 L L H X 1 OE1 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 A8 10 GND
FUNCTION TABLE
Inputs OE2 L L X H A L H X X L H Z Z Output Y
Z = High Impedance X = Don't Care
(Top View)
I I IIIIIII I IIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIII I I II I I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I I I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I
Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 35 75 750 500 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Plastic DIP SOIC Package Storage Temperature Range mW _C _C Tstg TL - 65 to + 150 260 Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP or SOIC Package
MAXIMUM RATINGS
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
II I I IIIIIIIIIIIIIIIIIIIIIII I II I II I I I II I I IIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII II I II IIIIIIIIIIIIIIIIIIIIII I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I II II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII II
Symbol VCC Parameter Min 4.5 0 Max 5.5 Unit V V DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Vin, Vout TA VCC Operating Temperature Range, All Package Types Input Rise/Fall Time (Figure 1) - 55 0 + 125 500 _C ns tr, tf
RECOMMENDED OPERATING CONDITIONS
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MC74HCT541A
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol VIH VIL VOH Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage Condition Vout = 0.1V or VCC - 0.1V |Iout| 20mA Vout = 0.1V or VCC - 0.1V |Iout| 20mA Vin = VIH or VIL |Iout| 20mA Vin = VIH or VIL VOL Maximum Low-Level Output Voltage Vin = VIH or VIL |Iout| 20mA Vin = VIH or VIL Iin IOZ Maximum Input Leakage Current Maximum 3-State Leakage Current Vin = VCC or GND Output in High Impedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND Iout = 0mA Vin = 2.4V, Any One Input Vin = VCC or GND, Other Inputs Iout = 0mA |Iout| 6.0mA |Iout| 6.0mA VCC V 4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5 Guaranteed Limit -55 to 25C 2.0 2.0 0.8 0.8 4.4 5.4 3.98 0.1 0.1 0.26 0.1 0.5 85C 2.0 2.0 0.8 0.8 4.4 5.4 3.84 0.1 0.1 0.33 1.0 5.0 125C 2.0 2.0 0.8 0.8 4.4 5.4 3.70 0.1 0.1 0.40 1.0 10.0 mA mA V Unit V V V
ICC DICC
Maximum Quiescent Supply Current (per Package) Additional Quiescent Supply Current
5.5
4 -55C
40
160
mA
25 to 125C 2.4 mA
5.5
2.9
1. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). 2. Total Supply Current = ICC + DICC.
AC CHARACTERISTICS (VCC = 5.0V, CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit Symbol tPLH, tPHL tPLZ, tPHZ tPZL, tPZH tTLH, tTHL Cin Cout Parameter Maximum Propagation Delay, Input A to Output Y (Figures 1 and 3) Maximum Propagation Delay, Output Enable to Output Y (Figures 2 and 4) Maximum Propagation Delay, Output Enable to Output Y (Figures 2 and 4) Maximum Output Transition Time, Any Output (Figures 1 and 3) Maximum Input Capacitance Maximum 3-State Output Capacitance (Output in High Impedance State) -55 to 25C 23 30 30 12 10 15 85C 28 34 34 15 10 15 125C 32 38 38 18 10 15 Unit ns ns ns ns pF pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Buffer)*
2f + I CC
55
pF
* Used to determine the no-load dynamic power consumption: PD = CPD VCC ON Semiconductor High-Speed CMOS Data Book (DL129/D).
VCC . For load considerations, see Chapter 2 of the
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MC74HCT541A
SWITCHING WAVEFORMS
tr 90% INPUT A tPLH 90% OUTPUT Y tTLH 1.3V 10% 1.3V 10%
tf 3.0V
GND tPHL
tTHL
Figure 1.
3.0V OE1 or OE2 1.3V tPZL OUTPUT Y 1.3V 10% tPZH OUTPUT Y 1.3V HIGH IMPEDANCE tPHZ 90% VOH VOL tPLZ 1.3V GND HIGH IMPEDANCE
Figure 2.
TEST CIRCUITS
TEST POINT OUTPUT DEVICE UNDER TEST C L* DEVICE UNDER TEST OUTPUT
TEST POINT 1kW CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ and tPZH.
C L*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 3.
Figure 4.
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MC74HCT541A
PIN DESCRIPTIONS
INPUTS
A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8, 9) -- Data input pins. Data on these pins appear in non-inverted form on the corresponding Y outputs, when the outputs are enabled.
CONTROLS
outputs are enabled and the device functions as a non-inverting buffer. When a high voltage is applied to either input, the outputs assume the high impedance state.
OUTPUTS
OE1, OE2 (PINS 1, 19) -- Output enables (active-low). When a low voltage is applied to both of these pins, the
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14, 13, 12, 11) -- Device outputs. Depending upon the state of the output enable pins, these outputs are either non-inverting outputs or high-impedance outputs.
LOGIC DETAIL
To 7 Other Buffers
One of Eight Buffers INPUT A
VCC
OUTPUT Y
OE1 OE2
ORDERING INFORMATION
Device MC74HCT541AN MC74HCT541ANG MC74HCT541ADW MC74HCT541ADWG MC74HCT541ADWR2 MC74HCT541ADWR2G MC74HCT541ADTR2 MC74HCT541ADTR2G MC74HCT541AFG MC74HCT541AFEL MC74HCT541AFELG Package PDIP-20 PDIP-20 (Pb-Free) SOIC-20 SOIC-20 (Pb-Free) SOIC-20 SOIC-20 (Pb-Free) TSSOP-20* TSSOP-20* SOEIAJ-20 (Pb-Free) SOEIAJ-20 SOEIAJ-20 (Pb-Free) 2000 / Tape & Reel 2500 / Tape & Reel 40 Units / Rail 1000 / Tape & Reel 38 Units / Rail 18 Units / Rail Shipping
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *These packages are inherently Pb-Free.
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MC74HCT541A
PACKAGE DIMENSIONS
PDIP-20 N SUFFIX CASE 738-03 ISSUE E
-A-
20 1 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
B
10
C
L
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
DIM A B C D E F G J K L M N
INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040
MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
SO-20 WB DW SUFFIX CASE 751D-05 ISSUE G
D
A
11 X 45 _
q
H
M
B
M
20
10X
0.25
E
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
1
10
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
h
18X
e
A1
T
C
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L
MC74HCT541A
PACKAGE DIMENSIONS
TSSOP-20 DT SUFFIX CASE 948E-02 ISSUE B
20X
K REF
M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
2X
L/2
L
PIN 1 IDENT 1 10
B -U-
J J1
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
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IIII IIII IIII
SECTION N-N 0.25 (0.010) M DETAIL E
20
11
K K1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
DIM A B C D F G H J J1 K K1 L M
MC74HCT541A
PACKAGE DIMENSIONS
SOEIAJ-20 F SUFFIX CASE 967-01 ISSUE A
20
11
LE Q1 M_ L DETAIL P
E HE
1
10
Z D e VIEW P A
c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.15 0.25 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.81 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.006 0.010 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.032
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC74HCT541A/D

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